The present invention relates generally to semiconductor manufacturing processes, and more particularly, to a method and system for the fabrication of a metal-over-metal(MOM) device structure for integrated circuit devices.
In integrated circuit design there are many applications of high-performance, on-chip capacitors. These applications include dynamic random access memories, voltage control oscillators, phase-lock loops, operational amplifiers, and switching capacitors. Such on-chip capacitors can also be used to decouple digital and analog integrated circuits from the noise of the rest of the electrical system.
The development of capacitor structures for integrated circuits has evolved from the initial parallel plate capacitor structures comprised of two conductive layers, to trench capacitor designs, MOM designs and more recently to the interdigitated metal finger structures. The parallel plate capacitor is typically comprised of a first and second layer of conductive material patterned to define top and bottom electrodes, with an intervening layer of a thin capacitor dielectric, the structure being isolated from the substrate by an underlying dielectric layer of thick field oxide. The bottom electrode typically comprises a layer of conductive material, often polysilicon, which forms other structures of the integrated circuit, such as gate electrodes or emitter structures of transistors. The second (top) electrode is defined thereon by a second conductive layer, typically another polysilicon layer. The capacitor dielectric is conventionally a thin silicon dioxide or silicon nitride layer. One of the well-known shortcomings of this parallel plate capacitor structure is the relatively large area of the chip required for each device which makes it a less area-efficient structure for advanced chip designs.
Trench capacitors are conventionally formed by depositing conductive and dielectric layers within trench regions defined in the substrate. Typically, an oval or circular vertical cylinder is etched into the substrate and concentrically arranged vertical electrodes are formed inside the trench. Trench capacitors exploit the downward vertical dimension into the substrate to create each capacitor device thereby reducing overall lateral dimensions of the chip which translates to reduced cost. A primary drawback to trench capacitors, however, is their lack of scalability as feature sizes shrink. Economically etching the trenches becomes difficult as the narrow trench openings and high aspect ratios cause extended trench etch times limited by diffusion of the etching chemistry into and out of the trenches.
More recently, interdigitated finger capacitor structures have been designed which exploit both the lateral and vertical electric fields between the electrodes thereby creating higher capacitance values per unit area than previous capacitor designs. Unfortunately, these designs have structural limitations which makes them less desirable to utilize within design libraries and limit their flexibility within circuit designs.
What is needed is a method to provide a unit cell capacitor structure that achieves high unit capacitance by exploiting both the lateral and vertical electric field components.